Download Algebraic Numbers (Pure & Applied Mathematics Monograph) by Paula Ribenboim PDF

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By Paula Ribenboim

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2 Hardwired lowly multiplexed data-paths (HLMD) A HLMD architecture consists of several pipelined data-paths which are only weakly programmable or even completely hardwired [Cat90] (Figure 3). In contrast to the EXUs occurring in an MP architecture, the internal composition 1 The methodology used in the CATHEDRAL-II/2nd script is a fnllnw up of the CATHEDRAL II methodolog~' reported previousb' [DeI\I88. Del'll90j. ----------... _--------DISTRIBUTED: MEMORIES ASU HIERARCHICAL FSM CONTROLLER Figure 3: HLMD architecture, containing customised ASUIJ, a hierarchical FSM controller and distributed memories.

In addition, the floorplanner determines the ordering of input/output pins for the glue-logic that will minimize the wire crossing between stack and glue-logic modules. In the final phase, the glue-logic module is generated by a striped layout generator [LiGa89], and the stack module is generated by generators using Mentor Graphics GDT tools. A global router then finishes the detailed routing between modules to generate the final layout. 9 VHDL Translators The selection of a description language or an interface language is difficult in a CAD framework where many tools must communicate and where a user may select to manually synthesize the design.

The major differences and the synthesis techniques applied will be analysed in some detail too. Note that in these scripts, scheduling and binding are only a few of the many tasks to be performed. Other tasks, like high-level memory management and word-length exploitations are to our knowledge at present ignored by conventional high-level synthesis approaches. It has to be stressed that the following tasks only address the part of the trajectory from an initial system specification to a detailed architecture.

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