By A. Potton (auth.)
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Extra info for An Introduction to Digital Logic
Discrete component NOR gate and indicates how two such gates, cross-coupled, form a discrete component R-S bistable circuit. 3 The clocked R-S flip-flop This system is a modification of the simple R-S flip-flop which incorporates a third input called the clock input. It is possible to set or reset the system via the S-R terminals only if the clock input is 1. 5. 5 It will be seen that A and 8 will always be 0 so long as Cis 0. When C becomes 1, A and 8 are equal to S and R respectively, allowing the systrm to be set or reset.
19 it follows that the required boolean expression describing the behaviour of the system is F=B·C·D+ A·C+A·B· D The system design is simply developed from this expression. 8 A second example Suppose the system specification given in the first example is changed and it is required that F should be 1 for N 1 greater than N 2 or N 1 = N 2 but be 0 for all other conditions. 3. 20 shows the various cell loopings. 9 'Don't care' situations We now suppose that in the previous problem, the specification for the system is again changed this time such that the value ofF for the condition N 1 = N 2 is irrelevant, that is it may be 0 or 1.
The alert reader may well have observed by now that the arrangement of cells shown in the map described above is not the only one which meets the essential requirement of only one digit difference between labels of adjacent cells. 4 it is apparent that we could choose column 1 as the column for which we have A = 0, 8 = 0 rather than C = 0, D =0. Row 1 could then have C = 0, D = 0 instead of A = 0, 8 = 0. We have thus interchanged the values of A, 8 and C, D in the rows and columns. 5. 3 will normally be used but any other arrangement which meets the requirement of one digit difference between adjacent cell labels is equally satisfactory.